beaglebone-black - Flipbook - Page 85
BeagleBone Black
Fig. 8.1: Expansion Board EEPROM Without Write Protect
8.1.4 EEPROM Address
In order for each cape to have a unique address, a board ID scheme is used that sets the address to be di昀昀erent
depending on the setting of the dipswitch or jumpers on the capes. A two position dipswitch or jumpers is used
to set the address pins of the EEPROM.
It is the responsibility of the user to set the proper address for each board and the position in the stack that the
board occupies has nothing to do with which board gets 昀椀rst choice on the usage of the expansion bus signals.
The process for making that determination and resolving con昀氀icts is left up to the SW and, as of this moment
in time, this method is a something of a mystery due to the new Device Tree methodology introduced in the
3.8 kernel.
Address line A2 is always tied high. This sets the allowable address range for the expansion cards to 0x54
to**0x57**. All other I2C addresses can be used by the user in the design of their capes. But, these addresses
must not be used other than for the board EEPROM information. This also allows for the inclusion of EEPROM
devices on the cape if needed without interfering with this EEPROM. It requires that A2 be grounded on the
EEPROM not used for cape identi昀椀cation.
8.1.5 I2C Bus
The EEPROMs on each expansion board are connected to I2C2 on connector P9 pins 19 and 20. For this reason
I2C2 must always be left connected and should not be changed by SW to remove it from the expansion header
pin mux settings. If this is done, the system will be unable to detect the capes.
The I2C signals require pullup resistors. Each board must have a 5.6K resistor on these signals. With four capes
installed this will result in an e昀昀ective resistance of 1.4K if all capes were installed and all the resistors used
were exactly 5.6K. As more capes are added the resistance is reduced to overcome capacitance added to the
signals. When no capes are installed the internal pullup resistors must be activated inside the processor to
prevent I2C timeouts on the I2C bus.
The I2C2 bus may also be used by capes for other functions such as I/O expansion or other I2C compatible
devices that do not share the same address as the cape EEPROM.
EEPROM **********************
The design in Figure 62 has the write protect disabled. If the write protect is not enabled, this does expose
the EEPROM to being corrupted if the I2C2 bus is used on the cape and the wrong address written to. It is
recommended that a write protection function be implemented and a Test Point be added that when grounded,
will allow the EEPROM to be written to. To enable write operation, Pin 7 of the EEPROM must be tied to ground.
When not grounded, the pin is HI via pullup resistor R210 and therefore write protected. Whether or not Write
Protect is provided is at the discretion of the cape designer.
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Chapter 8. Cape Board Support
