beaglebone-black - Flipbook - Page 59
BeagleBone Black
PHY_VDDCR Rail
The PHY_VDDCR rail originates inside the LAN8710A. Filter and bypass capacitors are used to 昀椀lter the rail.
Only circuitry inside the LAN8710A uses this rail.
SYS_RESET
The reset of the LAN8710A is controlled via the SYS_RESETn signal, the main board reset line.
Clock Signals
A crystal is used to create the clock for the LAN8710A. The processor uses the RMII_RXCLK signal to provide
the clocking for the data between the processor and the LAN8710A.
6.5 LAN8710A Mode Pins
There are mode pins on the LAN8710A that sets the operational mode for the PHY when coming out of reset.
These signals are also used to communicate between the processor and the LAN8710A. As a result, these
signals can be driven by the processor which can cause the PHY not to be initialized correctly. To ensure that
this does not happen, three low value pull up resistors are used. Figure 43 below shows the three mode pin
resistors.
Fig. 6.25: Ethernet PHY Mode Pins
This will set the mode to be 111, which enables all modes and enables auto-negotiation.
6.6 HDMI Interface
The BeagleBone Black has an onboard HDMI framer that converts the LCD signals and audio signals to drive a
HDMI monitor. The design uses an NXP TDA19988 HDMI Framer.
The following sections provide more detail into the design of this interface.
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Chapter 6. Detailed Hardware Design
