beaglebone-black - Flipbook - Page 51
BeagleBone Black
Chip Select Line: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All
commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with
multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA.
Input Data Mask Line: DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is
designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ.
On-die Termination Line: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3L SDRAM. When enabled in normal operation, ODT is only applied to each of the
following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT
input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA.
6.2.8 Power Rails
The DDR3L memory device and the DDR3 rails on the processor are supplied by the**TPS65217C**. Default
voltage is 1.5V but can be scaled down to 1.35V if desired.
6.2.9 VREF
The VREF signal is generated from a voltage divider on the**VDDS_DDR** rail that powers the processor DDR
rail and the DDR3L device itself. Figure 33 below shows the con昀椀guration of this signal and the connection to
the DDR3L memory device and the processor.
Fig. 6.14: DDR3L VREF Design
6.2.10
4GB eMMC Memory
The eMMC is a communication and mass data storage device that includes a Multi-MediaCard (MMC) interface,
a NAND Flash component, and a controller on an advanced 11-signal bus, which is compliant with the MMC
system speci昀椀cation. The nonvolatile eMMC draws no power to maintain stored data, delivers high performance
across a wide range of operating temperatures, and resists shock and vibration disruption.
One of the issues faced with SD cards is that across the di昀昀erent brands and even within the same brand, performance can vary. Cards use di昀昀erent controllers and di昀昀erent memories, all of which can have bad locations
that the controller handles. But the controllers may be optimized for reads or writes. You never know what you
will be getting. This can lead to varying rates of performance. The eMMC card is a known controller and when
coupled with the 8bit mode, 8 bits of data instead of 4, you get double the performance which should result in
quicker boot times.
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Chapter 6. Detailed Hardware Design
