beaglebone-black - Flipbook - Page 49
BeagleBone Black
Fig. 6.12: Board Reset Circuitry
the DDR3L devices can work down to
1.35V to achieve lower power. The DDR3L comes in a 96-BALL FBGA package with 0.8 mil pitch. Other standard
DDR3 devices can also be supported, but the DDR3L is the lower power device and was chosen for its ability
to work at 1.5V or 1.35V. The standard frequency that the DDR3L is run at on the board is 400MHZ.
6.2.7 DDR3L Memory Design
昀椀gure-32 is the schematic for the DDR3L memory device. Each of the groups of signals is described in the
following lines.
Address Lines: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective
bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the
mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop
(on-the-昀氀y) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop).
Bank Address Lines: BA[2:0] de昀椀ne the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command
is being applied. BA[2:0] de昀椀ne which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD
MODE command. BA[2:0] are referenced to VREFCA.
CK and CK# Lines: are di昀昀erential clock inputs. All address and control input signals are sampled on the
crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced
to the crossings of CK and CK#.
Clock Enable Line: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks
on the DRAM. The speci昀椀c circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM con昀椀guration
and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all
banks idle) or active power-down (row active in any bank). CKE is synchronous for powerdown entry and exit
and for self refresh entry. CKE is asynchronous for self refresh exit. Input bu昀昀ers (excluding CK, CK#, CKE,
RESET#, and ODT) are disabled during powerdown. Input bu昀昀ers (excluding CKE and RESET#) are disabled
during SELF REFRESH. CKE is referenced to VREFCA.
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Chapter 6. Detailed Hardware Design
