beaglebone-black - Flipbook - Page 47
BeagleBone Black
Table 6.3 – continued from previous page
Operating Systems
Linux,
Android,
Windows
Embedded
CE,QNX,ThreadX
MMC/SD
3
ARM MHz (Max.)
ARM MIPS (Max.)
Graphics Acceleration
Other Hardware Acceleration
On-Chip L1 Cache
On-Chip L2 Cache
Other On-Chip Memory
Display Options
General
Purpose
Memory
DRAM
275,500,600,800,1000
1000,1200,2000
1 3D
2 PRU-ICSS,Crypto Accelerator
64 KB (ARM Cortex-A8)
256 KB (ARM Cortex- A8)
128 KB
ADC
PWM (Ch)
eCAP
eQEP
8-ch 12-bit
3
3
3
RTC
I2C
McASP
1
3
2
LCD
1 16-bit (GPMC, NAND 昀氀ash,
NOR Flash, SRAM)
1 16-bit (LPDDR-400,DDR2532, DDR3-400)
2
SPI
DMA (Ch)
2
64-Ch EDMA
IO Supply (V)
1.8V(ADC), 3.3V
Operating Temperature Range (C)
40 to 90
USB Ports
6.2.3 Documentation
Full documentation for the processor can be found on the TI website at http://www.ti.com/product/am3358 for
the current processor used on the board. Make sure that you always use the latest datasheets and Technical
Reference Manuals (TRM).
6.2.4 Crystal Circuitry
6.2.5 Reset Circuitry
昀椀gure-31 is the board reset circuitry. The initial power on reset is generated by the TPS65217C power management IC. It also handles the reset for the Real Time Clock.
The board reset is the SYS_RESETn signal. This is connected to the NRESET_INOUT pin of the processor. This
pin can act as an input or an output. When the reset button is pressed, it sends a warm reset to the processor
and to the system.
On the revision A5D board, a change was made. On power up, the NRESET_INOUT signal can act as an output.
In this instance it can cause the SYS_RESETn line to go high prematurely. In order to prevent this, the PORZn
signal from the TPS65217C is connected to the SYS_RESETn line using an open drain bu昀昀er. These ensure that
the line does not momentarily go high on power up.
This change is also in all revisions after A5D.
DDR3L Memory
The BeagleBone Black uses a single MT41K256M16HA-125 512MB DDR3L device from Micron that interfaces
to the processor over 16 data lines, 16 address lines, and 14 control lines. On rev C we added the Kingston
KE4CN2H5A-A58 device as a source for the DDR3L device**.**
The following sections provide more details on the design.
6.2.6 Memory Device
The design supports the standard DDR3 and DDR3L x16 devices and is built using the DDR3L. A single x16
device is used on the board and there is no support for two x8 devices. The DDR3 devices work at 1.5V and
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Chapter 6. Detailed Hardware Design
