beaglebone-black - Flipbook - Page 45
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Fig. 6.8: TPS65217C Power Sequencing Timing
6.1.11
TPS65217C Power Up Process
Figure below shows the interface between the TPS65217C and the processor. It is a cut from the PDF form of
the schematic and re昀氀ects what is on the schematic.
Fig. 6.9: Power Processor Interfaces
When voltage is applied, DC or USB, the TPS65217C connects the power to the SYS output pin which drives
the switchers and LDOs in the TPS65217C.
At power up all switchers and LDOs are o昀昀 except for the VRTC LDO (1.8V), which provides power to the VRTC
rail and controls the RTC_PORZn input pin to the processor, which starts the power up process of the processor.
Once the RTC rail powers up, the RTC_PORZn pin, driven by the LDO_PGOOD signal from the TPS65217C, of
the processor is released.
Once the RTC_PORZn reset is released, the processor starts the initialization process. After the RTC stabilizes,
the processor launches the rest of the power up process by activating the PMIC_POWER_EN signal that is
connected to the TPS65217C which starts the TPS65217C power up process.
The LDO_PGOOD signal is provided by the**TPS65217C** to the processor. As this signal is 1.8V from the
TPS65217C by virtue of the TPS65217C VIO rail being set to 1.8V, and the RTC_PORZ signal on the processor
is 3.3V, a voltage level shifter, U4, is used. Once the LDOs and switchers are up on the TPS65217C, this signal
goes active releasing the processor. The LDOs on the TPS65217C are used to power the VRTC rail on the
processor.
6.1.12
Processor Control Interface
昀椀gure-28 above shows two interfaces between the processor and the TPS65217C used for control after the
power up sequence has completed.
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Chapter 6. Detailed Hardware Design
