beaglebone-black - Flipbook - Page 44
BeagleBone Black
VDD_MPU Rail
The VDD_MPU rail can deliver up to 1.2A. This rail is not accessible for use anywhere else on the board and
connects only to the processor. This rail defaults to 1.1V and can be scaled up to allow for higher frequency
operation. Changing of the voltage is set via the I2C interface from the processor.
VDDS_DDR Rail
The VDDS_DDR rail defaults to**1.5V** to support the DDR3L rails and can deliver up to 1.2A. It is possible to
adjust this voltage rail down to 1.35V for lower power operation of the DDR3L device. Only DDR3L devices can
support this voltage setting of 1.35V.
Power Sequencing
The power up process is consists of several stages and events. 昀椀gure-26 describes the events that make up
the power up process for the processor from the PMIC. This diagram is used elsewhere to convey additional
information. I saw no need to bust it up into smaller diagrams. It is from the processor datasheet supplied by
Texas Instruments.
Fig. 6.7: Power Rail Power Up Sequencing
昀椀gure-27 the voltage rail sequencing for the TPS65217C as it powers up and the voltages on each rail. The
power sequencing starts at 15 and then goes to one. That is the way the TPS65217C is con昀椀gured. You can
refer to the TPS65217C datasheet for more information.
6.1.10
Power LED
The power LED is a blue LED that will turn on once the TPS65217C has 昀椀nished the power up procedure. If you
ever see the LED 昀氀ash once, that means that the**TPS65217C** started the process and encountered an issue
that caused it to shut down. The connection of the LED is shown in 昀椀gure-25.
6.1. Power Section
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